// ******************************************************************************
// Copyright     :  Copyright (C) 2020, Hisilicon Technologies Co. Ltd.
// File name     :  hi1822_reg_offset.h
// Project line  :  IT Product Line
// Department    :  ICT Processor Chipset Development Department
// Version       :  V100
// Date          :
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V5.1
// file
// ******************************************************************************

#ifndef SM_REG_OFFSET_H
#define SM_REG_OFFSET_H

/* smrt_csr Base address of Module's Register */
#define CSR_SMRT_CSR_BASE (0xA00)

/* **************************************************************************** */
/*                      smrt_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_SMRT_CSR_SMRT_VERSION_REG (CSR_SMRT_CSR_BASE + 0x0) /* reserved for ECO */
#define CSR_SMRT_CSR_SMXR_CFG1_REG (CSR_SMRT_CSR_BASE + 0x4)    /* SMXR cofigure registers */
#define CSR_SMRT_CSR_SMXR_CFG0_REG (CSR_SMRT_CSR_BASE + 0x8)    /* SMXR cofigure registers */
#define CSR_SMRT_CSR_SMXT_CFG_REG                                                                              \
    (CSR_SMRT_CSR_BASE + 0xC) /* This is the Smart Memory Infra Cross Transmission (SMXT) module configuration \
                                 register.  The software use this register for debug. */
#define CSR_SMRT_CSR_SMXR_TM_GRT01_REG (CSR_SMRT_CSR_BASE + 0x10) /* Timer Group Routing table   element 0 and 1 */
#define CSR_SMRT_CSR_SMXR_TM_GRT23_REG (CSR_SMRT_CSR_BASE + 0x14) /* Timer Group Routing table   element 2 and 3 */
#define CSR_SMRT_CSR_SMRT_INT_VECTOR_REG (CSR_SMRT_CSR_BASE + 0x18)
#define CSR_SMRT_CSR_SMRT_INT_REG (CSR_SMRT_CSR_BASE + 0x1C)      /* SMRT interrupt data */
#define CSR_SMRT_CSR_SMRT_INT_MASK_REG (CSR_SMRT_CSR_BASE + 0x20) /* SMIR interrupt mask configuration */
#define CSR_SMRT_CSR_SMXR_REQ_MEM_CRT_ERR_REG \
    (CSR_SMRT_CSR_BASE + 0x24) /* ECC correctable memory detected on SMXR request memory */
#define CSR_SMRT_CSR_SMXR_REQ_MEM_UNCRT_ERR_REG \
    (CSR_SMRT_CSR_BASE + 0x28) /* ECC un-correctable memory detected on SMXR request memory */
#define CSR_SMRT_CSR_SMXR_MISS_SOP_EOP_ERR_REG (CSR_SMRT_CSR_BASE + 0x2C) /* SMXR received miss EOP API */
#define CSR_SMRT_CSR_SMXR_INDRECT_CTRL_REG (CSR_SMRT_CSR_BASE + 0x30)     /* indirect access address registers */
#define CSR_SMRT_CSR_SMXR_INDRECT_TIMEOUT_REG (CSR_SMRT_CSR_BASE + 0x34)  /* memory access timeout configure */
#define CSR_SMRT_CSR_SMXR_INDRECT_DATA_REG (CSR_SMRT_CSR_BASE + 0x38)     /* indirect access data registers */
#define CSR_SMRT_CSR_SMXT_CAP_CFG_REG                                                                                 \
    (CSR_SMRT_CSR_BASE +                                                                                              \
        0x3C) /* smxt capture fields configuration register .This is used for debug . The software can configure  \
                 capture conditions here .For example ,the software want to capture message and count matched message \
                 .The software can enable <cap_mode> field  and cofigure compare fields data here.(need to enable per \
                 field via <cap_sel_en> in <smxr_en_cnt> ) */
#define CSR_SMRT_CSR_SMXT_CAP_FIELD_CFG_REG                                                                           \
    (CSR_SMRT_CSR_BASE +                                                                                              \
        0x40) /* SMXT capture fields configuration register .This is used for debug . The software can configure  \
                 capture conditions here .For example ,the software want to capture message and count matched message \
                 .The software can enable <cap_mode> field  and cofigure compare fields data here.(need to enable per \
                 field via <cap_sel_en> in <smxr_en_cnt> ) */
#define CSR_SMRT_CSR_SMXT_CNT_CFG0_REG                                                                              \
    (CSR_SMRT_CSR_BASE + 0x44) /* SMXT mappable event counter controal . The software use this control to configure \
                                  expected counter mapping . */
#define CSR_SMRT_CSR_SMXT_CNT_CFG1_REG                                                                              \
    (CSR_SMRT_CSR_BASE + 0x48) /* SMXT mappable event counter controal . The software use this control to configure \
                                  expected counter mapping . */
#define CSR_SMRT_CSR_SMXT_CNT0_REG                                                                                   \
    (CSR_SMRT_CSR_BASE + 0x4C) /* SMXT physical counter 0.software can enable which events to be counted into it via \
                                  field <SMXT_en_cnt_0> in register <SMXT_CNT_CFG0> . */
#define CSR_SMRT_CSR_SMXT_CNT1_REG                                                                                   \
    (CSR_SMRT_CSR_BASE + 0x50) /* SMXT physical counter 1.software can enable which events to be counted into it via \
                                  field <SMXT_en_cnt_1> in register <SMXT_CNT_CFG0> . */
#define CSR_SMRT_CSR_SMXT_CNT2_REG                                                                                   \
    (CSR_SMRT_CSR_BASE + 0x54) /* SMXT physical counter 2.software can enable which events to be counted into it via \
                                  field <SMXT_en_cnt_2> in register <SMXT_CNT_CFG1> . */
#define CSR_SMRT_CSR_SMXT_CNT3_REG                                                                                   \
    (CSR_SMRT_CSR_BASE + 0x58) /* SMXT physical counter 3.software can enable which events to be counted into it via \
                                  field <SMXT_en_cnt_3> in register <SMXT_CNT_CFG1> . */
#define CSR_SMRT_CSR_SMXT_CRDT_CNT_REG (CSR_SMRT_CSR_BASE + 0x5C) /* smxt credit counter CTP registers */
#define CSR_SMRT_CSR_SMXT_FIFO_DEPTH0_REG \
    (CSR_SMRT_CSR_BASE + 0x60) /* FIFO depth CTP registers for SMXT FIFOs for SMF infra1 and infra0 */
#define CSR_SMRT_CSR_SMXT_FIFO_DEPTH1_REG \
    (CSR_SMRT_CSR_BASE + 0x68) /* FIFO depth CTP registers for SMXT FIFOs for SMF infra3 and Infra2 */
#define CSR_SMRT_CSR_TL0_Q_DEP_REG (CSR_SMRT_CSR_BASE + 0x6C) /* queue depth for API from TILE0 in SMXR */
#define CSR_SMRT_CSR_TL1_Q_DEP_REG (CSR_SMRT_CSR_BASE + 0x70) /* queue depth for API from TILE1 in SMXR */
#define CSR_SMRT_CSR_RQST_Q_DEP_REG \
    (CSR_SMRT_CSR_BASE + 0x74) /* queue depth for API from RING request channel in SMXR */
#define CSR_SMRT_CSR_RSP_Q_DEP_REG \
    (CSR_SMRT_CSR_BASE + 0x78) /* queue depth for API from RING request channel in SMXR */
#define CSR_SMRT_CSR_RQST_CRDT_CNT_REG (CSR_SMRT_CSR_BASE + 0x7C)     /* rqst channel credit counter  in SMXR */
#define CSR_SMRT_CSR_RESP_CRDT_CNT_REG (CSR_SMRT_CSR_BASE + 0x80)     /* rsponse channel credit counter in SMXR */
#define CSR_SMRT_CSR_SMXR_CNT0_REG (CSR_SMRT_CSR_BASE + 0x84)         /* Cnt for tile0 direct channel */
#define CSR_SMRT_CSR_SMXR_CNT1_REG (CSR_SMRT_CSR_BASE + 0x88)         /* Cnt for tile1 direct channel */
#define CSR_SMRT_CSR_SMXR_CNT2_REG (CSR_SMRT_CSR_BASE + 0x8C)         /* Cnt for ring request channel */
#define CSR_SMRT_CSR_SMXR_CNT3_REG (CSR_SMRT_CSR_BASE + 0x90)         /* Cnt for ring rsponse channel */
#define CSR_SMRT_CSR_SMXT_CTP_REG (CSR_SMRT_CSR_BASE + 0x94)          /* SMXT CTP registers */
#define CSR_SMRT_CSR_SMXR_CFG2_REG (CSR_SMRT_CSR_BASE + 0x98)         /* SMXR cofigure registers */
#define CSR_SMRT_CSR_SMXR_CFG3_REG (CSR_SMRT_CSR_BASE + 0x9C)         /* SMXR cofigure registers */
#define CSR_SMRT_CSR_CFG_MEM_CTRL_BUS0_REG (CSR_SMRT_CSR_BASE + 0xA0) /* RAM CTRL_BUS寄存器0 */
#define CSR_SMRT_CSR_CFG_MEM_CTRL_BUS1_REG (CSR_SMRT_CSR_BASE + 0xA4) /* RAM CTRL_BUS寄存器1 */
#define CSR_SMRT_CSR_CFG_MEM_CTRL_BUS2_REG (CSR_SMRT_CSR_BASE + 0xA8) /* RAM CTRL_BUS寄存器2 */
#define CSR_SMRT_CSR_CFG_MEM_CTRL_BUS3_REG (CSR_SMRT_CSR_BASE + 0xAC) /* RAM CTRL_BUS寄存器3 */
#define CSR_SMRT_CSR_CFG_MEM_CTRL_BUS4_REG (CSR_SMRT_CSR_BASE + 0xB0) /* RAM CTRL_BUS寄存器4 */
#define CSR_SMRT_CSR_SMXT_CFG2_REG (CSR_SMRT_CSR_BASE + 0xB4)         /* SMXT cofigure registers */

/* smir_csr Base address of Module's Register */
#define CSR_SMIR_CSR_BASE (0x100)

/* **************************************************************************** */
/*                      smir_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_SMIR_CSR_SMIR_VERSION_REG (CSR_SMIR_CSR_BASE + 0x0) /* reserved for ECO */
#define CSR_SMIR_CSR_SMIR_CFG_REG                                                                                      \
    (CSR_SMIR_CSR_BASE + 0x4) /* This is the Smart Memory Infra Receive (SMIR) module configuration register. Use this \
                                 register for debug. */
#define CSR_SMIR_CSR_SMIR_HASH_SEED0_REG                                                                               \
    (CSR_SMIR_CSR_BASE + 0x8) /* Hash function seed conifg register. This register used to change the original seed of \
                                 hash function. */
#define CSR_SMIR_CSR_SMIR_HASH_SEED1_REG                                                                               \
    (CSR_SMIR_CSR_BASE + 0xC) /* Hash function seed conifg register. This register used to change the original seed of \
                                 hash function. */
#define CSR_SMIR_CSR_SMIR_INT_VECTOR_REG (CSR_SMIR_CSR_BASE + 0x10)
#define CSR_SMIR_CSR_SMIR_INT_REG (CSR_SMIR_CSR_BASE + 0x14)         /* SMIR interrupt data */
#define CSR_SMIR_CSR_SMIR_INT_MASK_REG (CSR_SMIR_CSR_BASE + 0x18)    /* SMIR interrupt mask configuration */
#define CSR_SMIR_CSR_SMIR_ERR_SPEC_TH_REG (CSR_SMIR_CSR_BASE + 0x1C) /* Int[0] :specital thread drop for busy. */
#define CSR_SMIR_CSR_SMIR_REQ_MSG_ERR_REG (CSR_SMIR_CSR_BASE + 0x20) /* SMIR request channel message error register. \
                                                                      */
#define CSR_SMIR_CSR_SMIR_RESP_MSG_ERR_REG \
    (CSR_SMIR_CSR_BASE + 0x24) /* SMIR response channel message error register. */
#define CSR_SMIR_CSR_SMIR_MEM_ECC_CRT_ERR_REG (CSR_SMIR_CSR_BASE + 0x28)   /* smir memory ecc correctable error */
#define CSR_SMIR_CSR_SMIR_MEM_ECC_UNCRT_ERR_REG (CSR_SMIR_CSR_BASE + 0x2C) /* smir memory ecc uncorrectable error */
#define CSR_SMIR_CSR_SMIR_INDRECT_CTRL_REG (CSR_SMIR_CSR_BASE + 0x30)      /* indirect access address registers */
#define CSR_SMIR_CSR_SMIR_INDRECT_TIMEOUT_REG (CSR_SMIR_CSR_BASE + 0x34)   /* memory access timeout configure */
#define CSR_SMIR_CSR_SMIR_INDRECT_DATA_REG (CSR_SMIR_CSR_BASE + 0x38)      /* indirect access data registers */
#define CSR_SMIR_CSR_SMIR_CAP0_CFG_REG                                                                                \
    (CSR_SMIR_CSR_BASE +                                                                                              \
        0x3C) /* SMIR capture fields configuration register .This is used for debug . The software can configure  \
                 capture conditions here .For example ,the software want to capture message and count matched message \
                 .The software can enable <cap_mode> field  and cofigure compare fields data here.(need to enable per \
                 field via <cap_sel_en> in <smir_en_cnt> ) */
#define CSR_SMIR_CSR_SMIR_CAP1_CFG_REG                                                                                \
    (CSR_SMIR_CSR_BASE +                                                                                              \
        0x40) /* SMIR capture fields configuration register .This is used for debug . The software can configure  \
                 capture conditions here .For example ,the software want to capture message and count matched message \
                 .The software can enable <cap_mode> field  and cofigure compare fields data here. */
#define CSR_SMIR_CSR_SMIR_CAP2_CFG_REG                                                                                \
    (CSR_SMIR_CSR_BASE +                                                                                              \
        0x44) /* SMIR capture fields configuration register .This is used for debug . The software can configure  \
                 capture conditions here .For example ,the software want to capture message and count matched message \
                 .The software can enable <cap_mode> field  and cofigure compare fields data here. */
#define CSR_SMIR_CSR_SMIR_CAP3_CFG_REG                                                                                \
    (CSR_SMIR_CSR_BASE +                                                                                              \
        0x48) /* SMIR capture fields configuration register .This is used for debug . The software can configure  \
                 capture conditions here .For example ,the software want to capture message and count matched message \
                 .The software can enable <cap_mode> field  and cofigure compare fields data here. */
#define CSR_SMIR_CSR_SMIR_CAP4_CFG_REG                                                                                \
    (CSR_SMIR_CSR_BASE +                                                                                              \
        0x4C) /* SMIR capture fields configuration register .This is used for debug . The software can configure  \
                 capture conditions here .For example ,the software want to capture message and count matched message \
                 .The software can enable <cap_mode> field  and cofigure compare fields data here. */
#define CSR_SMIR_CSR_SMIR_CAP6_CFG_REG                                                                                \
    (CSR_SMIR_CSR_BASE +                                                                                              \
        0x50) /* SMIR capture fields configuration register .This is used for debug . The software can configure  \
                 capture conditions here .For example ,the software want to capture message and count matched message \
                 .The software can enable <cap_mode> field  and cofigure compare fields data here. */
#define CSR_SMIR_CSR_SMIR_EN_CNT_REG                                                                                \
    (CSR_SMIR_CSR_BASE + 0x54) /* SMIR mappable event counter controal . The software use this control to configure \
                                  expected counter mapping . */
#define CSR_SMIR_CSR_SMIR_CNT0_REG                                                                                   \
    (CSR_SMIR_CSR_BASE + 0x58) /* SMIR physical counter 0.software can enable which events to be counted into it via \
                                  field <smir_en_cnt_0> in register <SMIR_EN_CNT> . */
#define CSR_SMIR_CSR_SMIR_CNT1_REG                                                                                   \
    (CSR_SMIR_CSR_BASE + 0x5C) /* SMIR physical counter 1.software can enable which events to be counted into it via \
                                  field <smir_en_cnt_1> in register <SMIR_EN_CNT> . */
#define CSR_SMIR_CSR_SMIR_CNT2_REG                                                                                   \
    (CSR_SMIR_CSR_BASE + 0x60) /* SMIR physical counter 2.software can enable which events to be counted into it via \
                                  field <smir_en_cnt_2> in register <SMIR_EN_CNT> . */
#define CSR_SMIR_CSR_SMIR_CRDT_CNT_REG (CSR_SMIR_CSR_BASE + 0x64) /* SMIR credit counter CTP register */
#define CSR_SMIR_CSR_SMIR_CAP_FLIT0_DATA0_REG                                                                          \
    (CSR_SMIR_CSR_BASE + 0x68) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first    \
                                  flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \
                                  latest message.This is used for debug . Software can configure capture condition \
                                  in SMIR_CAP_CFG. And Read capture data here. */
#define CSR_SMIR_CSR_SMIR_CAP_FLIT0_DATA1_REG                                                                          \
    (CSR_SMIR_CSR_BASE + 0x70) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first    \
                                  flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \
                                  latest message.This is used for debug . Software can configure capture condition \
                                  in SMIR_CAP_CFG. And Read capture data here. */
#define CSR_SMIR_CSR_SMIR_CAP_FLIT1_DATA0_REG                                                                          \
    (CSR_SMIR_CSR_BASE + 0x78) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first    \
                                  flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \
                                  latest message.This is used for debug . Software can configure capture condition \
                                  in SMIR_CAP_CFG. And Read capture data here. */
#define CSR_SMIR_CSR_SMIR_CAP_FLIT1_DATA1_REG                                                                          \
    (CSR_SMIR_CSR_BASE + 0x80) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first    \
                                  flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \
                                  latest message.This is used for debug . Software can configure capture condition \
                                  in SMIR_CAP_CFG. And Read capture data here. */
#define CSR_SMIR_CSR_SMIR_CAP_FLIT2_DATA0_REG                                                                          \
    (CSR_SMIR_CSR_BASE + 0x88) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first    \
                                  flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \
                                  latest message.This is used for debug . Software can configure capture condition \
                                  in SMIR_CAP_CFG. And Read capture data here. */
#define CSR_SMIR_CSR_SMIR_CAP_FLIT2_DATA1_REG                                                                          \
    (CSR_SMIR_CSR_BASE + 0x90) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first    \
                                  flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \
                                  latest message.This is used for debug . Software can configure capture condition \
                                  in SMIR_CAP_CFG. And Read capture data here. */
#define CSR_SMIR_CSR_SMIR_CAP_FLIT3_DATA0_REG                                                                          \
    (CSR_SMIR_CSR_BASE + 0x98) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first    \
                                  flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \
                                  latest message.This is used for debug . Software can configure capture condition \
                                  in SMIR_CAP_CFG. And Read capture data here. */
#define CSR_SMIR_CSR_SMIR_CAP_FLIT3_DATA1_REG                                                                          \
    (CSR_SMIR_CSR_BASE + 0xA0) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first    \
                                  flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \
                                  latest message.This is used for debug . Software can configure capture condition \
                                  in SMIR_CAP_CFG. And Read capture data here. */
#define CSR_SMIR_CSR_SMIR_CAP_FLIT4_DATA0_REG                                                                          \
    (CSR_SMIR_CSR_BASE + 0xA8) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first    \
                                  flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \
                                  latest message.This is used for debug . Software can configure capture condition \
                                  in SMIR_CAP_CFG. And Read capture data here. */
#define CSR_SMIR_CSR_SMIR_CAP_FLIT4_DATA1_REG                                                                          \
    (CSR_SMIR_CSR_BASE + 0xB0) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first    \
                                  flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \
                                  latest message.This is used for debug . Software can configure capture condition \
                                  in SMIR_CAP_CFG. And Read capture data here. */
#define CSR_SMIR_CSR_SMIR_CAP_FLIT5_DATA0_REG                                                                          \
    (CSR_SMIR_CSR_BASE + 0xB8) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first    \
                                  flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \
                                  latest message.This is used for debug . Software can configure capture condition \
                                  in SMIR_CAP_CFG. And Read capture data here. */
#define CSR_SMIR_CSR_SMIR_CAP_FLIT5_DATA1_REG                                                                          \
    (CSR_SMIR_CSR_BASE + 0xC0) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first    \
                                  flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \
                                  latest message.This is used for debug . Software can configure capture condition \
                                  in SMIR_CAP_CFG. And Read capture data here. */
#define CSR_SMIR_CSR_SMIR_CAP_FLIT0_DATA2_REG                                                                          \
    (CSR_SMIR_CSR_BASE + 0xC8) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first    \
                                  flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \
                                  latest message.This is used for debug . Software can configure capture condition \
                                  in SMIR_CAP_CFG. And Read capture data here. */
#define CSR_SMIR_CSR_SMIR_CAP_FLIT1_DATA2_REG                                                                          \
    (CSR_SMIR_CSR_BASE + 0xCC) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first    \
                                  flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \
                                  latest message.This is used for debug . Software can configure capture condition \
                                  in SMIR_CAP_CFG. And Read capture data here. */
#define CSR_SMIR_CSR_SMIR_CAP_FLIT2_DATA2_REG                                                                          \
    (CSR_SMIR_CSR_BASE + 0xD0) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first    \
                                  flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \
                                  latest message.This is used for debug . Software can configure capture condition \
                                  in SMIR_CAP_CFG. And Read capture data here. */
#define CSR_SMIR_CSR_SMIR_CAP_FLIT3_DATA2_REG                                                                          \
    (CSR_SMIR_CSR_BASE + 0xD4) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first    \
                                  flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \
                                  latest message.This is used for debug . Software can configure capture condition \
                                  in SMIR_CAP_CFG. And Read capture data here. */
#define CSR_SMIR_CSR_SMIR_CAP_FLIT4_DATA2_REG                                                                          \
    (CSR_SMIR_CSR_BASE + 0xD8) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first    \
                                  flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \
                                  latest message.This is used for debug . Software can configure capture condition \
                                  in SMIR_CAP_CFG. And Read capture data here. */
#define CSR_SMIR_CSR_SMIR_CAP_FLIT5_DATA2_REG                                                                          \
    (CSR_SMIR_CSR_BASE + 0xDC) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first    \
                                  flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \
                                  latest message.This is used for debug . Software can configure capture condition \
                                  in SMIR_CAP_CFG. And Read capture data here. */
#define CSR_SMIR_CSR_SMIR_CFG1_REG                                                                                 \
    (CSR_SMIR_CSR_BASE + 0xE0) /* This is the Smart Memory Infra Receive (SMIR) module configuration register. Use \
                                  this register for debug. */

/* smeg0_abuf0_csr Base address of Module's Register */
#define CSR_SMEG0_ABUF0_CSR_BASE (0x200)

/* **************************************************************************** */
/*                      smeg0_abuf0_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_SMEG0_ABUF0_CSR_SMEG0_ABUF0_VERSION_REG (CSR_SMEG0_ABUF0_CSR_BASE + 0x0) /* reserved for ECO */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_GRW_WM_0_REG \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x4) /* This is the Sm Abuf0 grow watermark config register. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_GRW_WM_1_REG \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x8) /* This is the Sm abuf0 grow watermark config register. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_GRW_WM_2_REG \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0xC) /* This is the Sm abuf0 grow watermark config register. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_GRW_WM_3_REG \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x10) /* This is the Sm abuf0 grow watermark config register. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_GRW_WM_4_REG \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x14) /* This is the Sm abuf0 grow watermark config register. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_GRW_WM_5_REG \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x18) /* This is the Sm abuf0 grow watermark config register. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_GRW_WM_6_REG \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x1C) /* This is the Sm abuf0 grow watermark config register. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_SHK_WM_0_REG \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x20) /* This is the Sm abuf0 shrink watermark config register. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_SHK_WM_1_REG \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x24) /* This is the Sm abuf0 shrink watermark config register. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_SHK_WM_2_REG \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x28) /* This is the Sm abuf0 shrink watermark config register. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_SHK_WM_3_REG \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x2C) /* This is the Sm abuf0 shrink watermark config register. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_SHK_WM_4_REG \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x30) /* This is the Sm abuf0 shrink watermark config register. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_SHK_WM_5_REG \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x34) /* This is the Sm abuf0 shrink watermark config register. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_SHK_WM_6_REG \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x38) /* This is the Sm abuf0 shrink watermark config register. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_FLRC_ATTR_REG                                                                    \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x3C) /* This is the free list reclaim attribute config register.This is used to set \
                                         up the reclaim operation on one free list. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_FLRC_NUM_REG                                                                       \
    (CSR_SMEG0_ABUF0_CSR_BASE +                                                                                        \
        0x40) /* This is the Sm abuf0 free list reclaim number config register.This is used to set the total number of \
                 free nodes that the software wants to get from the particular free list.This register must be set     \
                 before the reclaim operation is set up. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_FLRC_BOUND_U_REG                                                                 \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x44) /* This is the Sm abuf0 reclaim upper boundary config register.This is used to \
                                         set the upper boundary of the reclaim region. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_FLRC_BOUND_L_REG                                                                   \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x48) /* Sm abuf0 reclaim lower boundary config register. This register is used to set \
                                         the lower boundary of the reclaim region. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_PF_LIFO_CLR_REG                                                                   \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x4C) /* This is the Sm abuf0 pre-fetch lifo clear register.This is used to clear any \
                                         pfetch lifos if software wants.(here lifo means Last in first out) */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_MEM_CFG_REG \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x50) /* This is the Sm abuf0 parity bit check enable config register. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_INT_VECTOR_REG                                                                   \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x54) /* This is the Smart Memory (SM) abuf0 interrupt vector  register.This is used \
                                         to determine the CP interrupt address, disable and enable an interrupt      \
                                         report,and provide the  total status of an abuf0 interrupt. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_INT_REG                                                                          \
    (CSR_SMEG0_ABUF0_CSR_BASE +                                                                                      \
        0x58) /* This is the SM abuf0 interrupt data register.This is used to record the history of the interrupt    \
                 status since the last clear operation. Software can use this register to let the CP know, which CSR \
                 module, or group of CSR modules, requested the interrupt. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_INT_MASK_REG                                                                      \
    (CSR_SMEG0_ABUF0_CSR_BASE +                                                                                       \
        0x5C) /* This is the SM abuf0 interrupt mask register.This is used to mask the bits of the interrupt register \
                 that should not be reported to an upper level.Software can use this register to mask corresponding   \
                 bits if they do not want those bits reporting to an upper level. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_PBERR_REG                                                                     \
    (CSR_SMEG0_ABUF0_CSR_BASE +                                                                                   \
        0x60) /* This is the ireq_list's output data Parity Bit Error interrupt register.Software can get related \
                 ireq_list information from this register. This register is used for debug. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_FL_UFLOW_ERR_REG                                                                   \
    (CSR_SMEG0_ABUF0_CSR_BASE +                                                                                        \
        0x64) /* This is the free list underflow error interrupt register.This register is used to record the          \
                 underflow status of 32 free lists.Any free lists are in underflow status,this register will           \
                 trigger.This register is used for debug.  Software can use this register to scan the status of 32 \
                 free lists. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_FL_OFLOW_ERR_REG                                                                  \
    (CSR_SMEG0_ABUF0_CSR_BASE +                                                                                       \
        0x68) /* This is the free list overflow error interrupt register.This register is used to record the overflow \
                 status of 32 free lists.If any free lists are in an  overflow state,this register will trigger.This  \
                 register is used for debug.  Software can use this register to scan the status of the 32 free    \
                 lists. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_FL_TAIL_MISS_ERR_REG                                                           \
    (CSR_SMEG0_ABUF0_CSR_BASE +                                                                                    \
        0x6C) /* This is the tail missed error interrupt register.This is used to capture information of regarding \
                 list whose tail pointer is not equal to the last pointer of the link list,when the free node      \
                 group(including the last pointer) is load from outside DDR.This register is used for debug. */
#define CSR_SMEG0_ABUF0_CSR_SMEG0_ABUF_INDRECT_CTRL_REG \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x70) /* indirect access address registers */
#define CSR_SMEG0_ABUF0_CSR_SMEG0_ABUF_INDRECT_TIMEOUT_REG \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x74) /* memory access timeout configure */
#define CSR_SMEG0_ABUF0_CSR_SMEG0_ABUF_INDRECT_DATA_REG \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x78) /* indirect access data registers */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_DIS_ALLOC_REG                                                                \
    (CSR_SMEG0_ABUF0_CSR_BASE +                                                                                  \
        0x7C) /* This is the SM Abuf0 disable allocation config register.This is used by software to disable the \
                 allocate operation if you do not want to release any free nodes from the particular list. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_DIS_DE_ALLOC_REG                                                              \
    (CSR_SMEG0_ABUF0_CSR_BASE +                                                                                   \
        0x80) /* This is the SM Abuf0 de_allocate disable config register.This is used by software to disable the \
                 de-allocate operation if you do not want to put any free nodes to the particular  list. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_FLRC_ST_REG                                                                     \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x84) /* This is the Sm abuf0 free list reclaim status register.This is used by the \
                                         software to scan the reclaimed working state. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_EMPTY_FL_REG                                                                       \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x88) /* This is the Sm abuf0 free list empty status register.This is used by software \
                                         to scan whether regarding list is empty or not. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_FULL_FL_REG                                                                       \
    (CSR_SMEG0_ABUF0_CSR_BASE +                                                                                       \
        0x8C) /* This is the Sm abuf0 free list full/almost full status register.This is used by the software to scan \
                 whether the list is full, almost full, or none of the above. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_ST_WM_GROW_REG                                                                   \
    (CSR_SMEG0_ABUF0_CSR_BASE +                                                                                      \
        0x90) /* This is the Sm abuf0 free list grow watermark status register.This is used by the softeware to scan \
                 whether the free list is in status that need to grow. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_ST_WM_SHRINK_REG                                                                  \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x94) /* This is the Sm abuf0 free list shrink watermark status register.This is used \
                                         by the softeware to scan whether the free list is in a shrink status. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_CNT_SEL0_REG                                                                 \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x98) /* This is the Sm abuf0 csr counter select config register.This is used to \
                                         select which free list must be counted. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_CNT_SEL1_REG                                                                    \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0x9C) /* Sm abuf ireq list status register.Sw can use this register to judge if the \
                                         request queue is empty or not. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_COUNTER0_REG                                                                      \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0xA0) /* This is the Sm abuf0 allocate free node count register.This is used to count \
                                         the free nodes that have been allocated successfully by abuf0. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_COUNTER1_REG                                                                   \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0xA4) /* This is the Sm abuf0 de-allocate free node count register.This is used to \
                                         count the free nodes that have been de-allocated successfully by abuf0. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_COUNTER2_REG                                                                    \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0xA8) /* This is the allocate failed operation count register.This is used to count \
                                         the total number of failed allocate operation attempts. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_COUNTER3_REG                                                                       \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0xAC) /* This is the Sm abuf0 de-allocate failed operation count register.This is used \
                                         to count the total number of failed de-allocate operation attempts. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_COUNTER4_REG                                                                    \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0xB0) /* This is the Sm abuf0 total pre-fetch load operation count register.This is \
                                         used to count the total number of pre-fetched load operations. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_COUNTER5_REG                                                                     \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0xB4) /* This is the Sm abuf0 total pre-fetch store operation count register.This is \
                                         used to count the total pre-fetched  store operations. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_PFETCH_FLAG_REG                                                                \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0xB8) /* Sm abuf pre-fetch load/store setup flag.This is used to record which free \
                                         list has initiated pre-fetch load/store operation. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_IREQ_LIST_STA_REG                                                               \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0xBC) /* Sm abuf ireq list status register.Sw can use this register to judge if the \
                                         request queue is empty or not. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TAIL_MISS0_REG                                                                     \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0xC0) /* This is the SM abuf0 tail miss capture register.  This is used to capture the \
                                         information of the tail-missed free list. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TAIL_MISS1_REG                                                                     \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0xC8) /* This is the SM abuf0 tail miss capture register.  This is used to capture the \
                                         information of the tail-missed free list. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_CNT_LIFO_PFETCH_0_REG                                                             \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0xD0) /* This is the Sm abuf0 pfetch lifo node number register.This is used to record \
                                         the free node number in each pfetch lifo. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_CNT_LIFO_PFETCH_1_REG                                                             \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0xD8) /* This is the Sm abuf0 pfetch lifo node number register.This is used to record \
                                         the free node number in each pfetch lifo. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_CNT_LIFO_PFETCH_2_REG                                                             \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0xE0) /* This is the Sm abuf0 pfetch lifo node number register.This is used to record \
                                         the free node number in each pfetch lifo. */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_ECC_CFG_REG \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0xE4) /* SMEG0_ABUF ECC function configration register */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_ECC_1B_ERR_INT_REG \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0xE8) /* 1 bit error sticky register */
#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_ECC_2B_ERR_INT_REG \
    (CSR_SMEG0_ABUF0_CSR_BASE + 0xEC) /* 2 bit error sticky register */

/* smeg0_aget_csr Base address of Module's Register */
#define CSR_SMEG0_AGET_CSR_BASE (0x300)

/* **************************************************************************** */
/*                      smeg0_aget_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_SMEG0_AGET_CSR_SMEG0_AGET_VERSION_REG (CSR_SMEG0_AGET_CSR_BASE + 0x0)    /* reserved for ECO */
#define CSR_SMEG0_AGET_CSR_SMEG0_AGET_CFG_REG (CSR_SMEG0_AGET_CSR_BASE + 0x4)        /* age table configure registers */
#define CSR_SMEG0_AGET_CSR_SMEG0_AGET_INT_VECTOR_REG (CSR_SMEG0_AGET_CSR_BASE + 0x8) /* interrupt vector */
#define CSR_SMEG0_AGET_CSR_SMEG0_AGET_INT_REG (CSR_SMEG0_AGET_CSR_BASE + 0xC)        /* interrupt data */
#define CSR_SMEG0_AGET_CSR_SMEG0_AGET_INT_MASK_REG (CSR_SMEG0_AGET_CSR_BASE + 0x10)  /* interrupt mask */
#define CSR_SMEG0_AGET_CSR_SMEG0_AGET_MEM_PRTY_ERR_REG \
    (CSR_SMEG0_AGET_CSR_BASE + 0x14) /* SMEG0_AGET age flag memory parity error */
#define CSR_SMEG0_AGET_CSR_SMEG0_AGET_BOUNDARY_ERR_REG \
    (CSR_SMEG0_AGET_CSR_BASE + 0x18) /* SMEG0_AGET operation is out of the table boundary */
#define CSR_SMEG0_AGET_CSR_SMEG0_AGET_INDRECT_CTRL_REG \
    (CSR_SMEG0_AGET_CSR_BASE + 0x1C) /* indirect access address registers */
#define CSR_SMEG0_AGET_CSR_SMEG0_AGET_INDRECT_TIMEOUT_REG \
    (CSR_SMEG0_AGET_CSR_BASE + 0x20) /* memory access timeout configure */
#define CSR_SMEG0_AGET_CSR_SMEG0_AGET_INDRECT_DATA_REG \
    (CSR_SMEG0_AGET_CSR_BASE + 0x24)                                               /* indirect access data registers */
#define CSR_SMEG0_AGET_CSR_SMEG_CORE_MEM_INIT_REG (CSR_SMEG0_AGET_CSR_BASE + 0x28) /* smeg core memory init done flag \
                                                                                    */
#define CSR_SMEG0_AGET_CSR_SMEG0_CNT0_REG (CSR_SMEG0_AGET_CSR_BASE + 0x2C)         /* SMEG0 Counter 0 */
#define CSR_SMEG0_AGET_CSR_SMEG0_CNT1_REG (CSR_SMEG0_AGET_CSR_BASE + 0x30)         /* SMEG0 Counter 1 */

/* smeg0_lu_csr Base address of Module's Register */
#define CSR_SMEG0_LU_CSR_BASE (0x400)

/* **************************************************************************** */
/*                      smeg0_lu_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_SMEG0_LU_CSR_SMEG0_LU_VERSION_REG (CSR_SMEG0_LU_CSR_BASE + 0x0) /* reserved for ECO */
#define CSR_SMEG0_LU_CSR_SMEG0_LU_CHK_ENABLE_CFG_REG \
    (CSR_SMEG0_LU_CSR_BASE + 0x4) /* configuration register for memory check enbale */
#define CSR_SMEG0_LU_CSR_SMEG0_LU_INT_VECTOR_REG (CSR_SMEG0_LU_CSR_BASE + 0x8) /* interrupt vector */
#define CSR_SMEG0_LU_CSR_SMEG0_LU_INT_REG (CSR_SMEG0_LU_CSR_BASE + 0xC)        /* interrupt data */
#define CSR_SMEG0_LU_CSR_SMEG0_LU_INT_MASK_REG (CSR_SMEG0_LU_CSR_BASE + 0x10)  /* interrupt mask */
#define CSR_SMEG0_LU_CSR_SMEG0_LU_PIPE0_MEM_ECC_CRT_ERR_REG \
    (CSR_SMEG0_LU_CSR_BASE + 0x14) /* SMEG0_LOOKUP_PIPE0MEM ECC 1bit error */
#define CSR_SMEG0_LU_CSR_SMEG0_LU_PIPE0_MEM_ECC_UNCRT_ERR_REG \
    (CSR_SMEG0_LU_CSR_BASE + 0x18) /* SMEG0_LOOKUP_PIPE0MEM ECC multi-bit error */
#define CSR_SMEG0_LU_CSR_SMEG0_LU_PIPE1_MEM_ECC_CRT_ERR_REG \
    (CSR_SMEG0_LU_CSR_BASE + 0x1C) /* SMEG0_LOOKUP_PIPE1MEM ECC 1bit error */
#define CSR_SMEG0_LU_CSR_SMEG0_LU_PIPE1_MEM_ECC_UNCRT_ERR_REG \
    (CSR_SMEG0_LU_CSR_BASE + 0x20) /* SMEG0_LOOKUP_PIPE1MEM ECC multi-bit error */
#define CSR_SMEG0_LU_CSR_SMEG0_LU_FLITFIFO_MEM_ECC_CRT_ERR_REG \
    (CSR_SMEG0_LU_CSR_BASE + 0x24) /* SMEG0_LU_FLITFIFO 1bit error */
#define CSR_SMEG0_LU_CSR_SMEG0_LU_FLITFIFO_MEM_ECC_UNCRT_ERR_REG \
    (CSR_SMEG0_LU_CSR_BASE + 0x28) /* SMEG0_LU_FLITFIFO multi-bit error */
#define CSR_SMEG0_LU_CSR_SMEG0_LU_SW_ERR_REG \
    (CSR_SMEG0_LU_CSR_BASE + 0x2C) /* BTREE engine detected software fatal error */
#define CSR_SMEG0_LU_CSR_SMEG0_LU_INDRECT_CTRL_REG \
    (CSR_SMEG0_LU_CSR_BASE + 0x30) /* indirect access address registers */
#define CSR_SMEG0_LU_CSR_SMEG0_LU_INDRECT_TIMEOUT_REG \
    (CSR_SMEG0_LU_CSR_BASE + 0x34)                                                /* memory access timeout configure */
#define CSR_SMEG0_LU_CSR_SMEG0_LU_INDRECT_DATA_REG (CSR_SMEG0_LU_CSR_BASE + 0x38) /* indirect access data registers */
#define CSR_SMEG0_LU_CSR_SMEG0_LU_ERR_INJ_CFG_REG                                                              \
    (CSR_SMEG0_LU_CSR_BASE +                                                                                   \
        0x3C) /* configuration register for error injection of FIFO memories. FIFO doesn't support CSR access. \
                 Software can set error inject enable bit to test error handling. */
#define CSR_SMEG0_LU_CSR_SMEG0_LU_CNT_CFG_REG \
    (CSR_SMEG0_LU_CSR_BASE + 0x40)                                        /* counter related configuration register */
#define CSR_SMEG0_LU_CSR_SMEG0_LU_CNT0_REG (CSR_SMEG0_LU_CSR_BASE + 0x44) /* counter0 */
#define CSR_SMEG0_LU_CSR_SMEG0_LU_CNT1_REG (CSR_SMEG0_LU_CSR_BASE + 0x48) /* counter1 */
#define CSR_SMEG0_LU_CSR_SMEG0_LU_CNT2_REG (CSR_SMEG0_LU_CSR_BASE + 0x4C) /* counter2 */
#define CSR_SMEG0_LU_CSR_SMEG0_LU_CNT3_REG (CSR_SMEG0_LU_CSR_BASE + 0x50) /* counter3 */
#define CSR_SMEG0_LU_CSR_SMEG0_LU_CTP_REG \
    (CSR_SMEG0_LU_CSR_BASE + 0x54) /* SMEG0 Profile Register for performance monitor. */

/* smeg1_csr Base address of Module's Register */
#define CSR_SMEG1_CSR_BASE (0x500)

/* **************************************************************************** */
/*                      smeg1_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_SMEG1_CSR_SMEG1_VERSION_REG (CSR_SMEG1_CSR_BASE + 0x0) /* reserved for ECO */
#define CSR_SMEG1_CSR_SMEG1_CFG0_REG                                                                                \
    (CSR_SMEG1_CSR_BASE + 0x4) /* Smart Memory Infra Engine Group1 (SMEG1) configuration register . This is used to \
                                  configure  additional features,  and for debug. */
#define CSR_SMEG1_CSR_SMEG1_CFG1_REG \
    (CSR_SMEG1_CSR_BASE + 0x8) /* Smart Memory Infra Engine Group1 (SMEG1) configuration register . */
#define CSR_SMEG1_CSR_SMEG1_RUNAWAY_CFG_REG                                                                            \
    (CSR_SMEG1_CSR_BASE + 0xC) /* Smart Memory Infra Engine Group1 (SMEG1) Runaway sampling count configuration        \
                                  register.   In the normal operation, this can be used as a watch dog timer for 16 or \
                                  64 threads in a smart memory tile. */
#define CSR_SMEG1_CSR_SMEG1_THREAD_ENABLE_CFG_REG                                                        \
    (CSR_SMEG1_CSR_BASE + 0x10) /* Thread enable configure; bitmap for 16/32/64 thread in smeg1;Refer to \
                                   "SMEG1_THREAD_ENABLE_CFG2" for thread[63:32] enable; */
#define CSR_SMEG1_CSR_SMEG1_TM_TS_FAST2_REG (CSR_SMEG1_CSR_BASE + 0x14) /* timer wheel control info */
#define CSR_SMEG1_CSR_SMEG1_TM_TS_FAST3_REG (CSR_SMEG1_CSR_BASE + 0x18) /* TIMER engine wheel control info */
#define CSR_SMEG1_CSR_SMEG1_TM_TS_SLOW0_REG (CSR_SMEG1_CSR_BASE + 0x1C) /* TIMER engine control info */
#define CSR_SMEG1_CSR_SMEG1_TM_TS_SLOW1_REG (CSR_SMEG1_CSR_BASE + 0x20) /* TIMER engine control info */
#define CSR_SMEG1_CSR_SMEG1_TM_TMT_CFG7_REG (CSR_SMEG1_CSR_BASE + 0x24) /* TIMER engine type cfg */
#define CSR_SMEG1_CSR_SMEG1_TM_TMT_CFG6_REG (CSR_SMEG1_CSR_BASE + 0x28) /* TIMER engine type cfg */
#define CSR_SMEG1_CSR_SMEG1_TM_TMT_CFG5_REG (CSR_SMEG1_CSR_BASE + 0x2C) /* TIMER engine type cfg */
#define CSR_SMEG1_CSR_SMEG1_TM_TMT_CFG4_REG (CSR_SMEG1_CSR_BASE + 0x30) /* TIMER engine type cfg */
#define CSR_SMEG1_CSR_SMEG1_TM_TMT_CFG3_REG (CSR_SMEG1_CSR_BASE + 0x34) /* TIMER engine type cfg */
#define CSR_SMEG1_CSR_SMEG1_TM_TMT_CFG2_REG (CSR_SMEG1_CSR_BASE + 0x38) /* TIMER engine type cfg */
#define CSR_SMEG1_CSR_SMEG1_TM_TMT_CFG1_REG (CSR_SMEG1_CSR_BASE + 0x3C) /* TIMER engine type cfg */
#define CSR_SMEG1_CSR_SMEG1_TM_TMT_CFG0_REG (CSR_SMEG1_CSR_BASE + 0x40) /* TIMER engine type cfg */
#define CSR_SMEG1_CSR_SMEG1_INT_VECTOR_REG (CSR_SMEG1_CSR_BASE + 0x44)
#define CSR_SMEG1_CSR_SMEG1_INT_REG (CSR_SMEG1_CSR_BASE + 0x48)
#define CSR_SMEG1_CSR_SMEG1_INT_MASK_REG (CSR_SMEG1_CSR_BASE + 0x4C)
#define CSR_SMEG1_CSR_SMEG1_ENGINE_SW_ERR_REG \
    (CSR_SMEG1_CSR_BASE +                     \
        0x50) /* This is Smart Memory Infra Engine Group1 (SMEG1) engine software error log register. */
#define CSR_SMEG1_CSR_SMEG1_ERR0_REG (CSR_SMEG1_CSR_BASE + 0x54)      /* error register 0 */
#define CSR_SMEG1_CSR_SMEG1_ERR0_MASK_REG (CSR_SMEG1_CSR_BASE + 0x58) /* error register 1 */
#define CSR_SMEG1_CSR_SMEG1_ERR1_REG (CSR_SMEG1_CSR_BASE + 0x5C)
#define CSR_SMEG1_CSR_SMEG1_ERR1_MASK_REG (CSR_SMEG1_CSR_BASE + 0x60)
#define CSR_SMEG1_CSR_SMEG1_INDRECT_CTRL_REG (CSR_SMEG1_CSR_BASE + 0x64)    /* indirect access address registers */
#define CSR_SMEG1_CSR_SMEG1_INDRECT_TIMEOUT_REG (CSR_SMEG1_CSR_BASE + 0x68) /* memory access timeout configure */
#define CSR_SMEG1_CSR_SMEG1_INDRECT_DATA_REG (CSR_SMEG1_CSR_BASE + 0x6C)    /* indirect access data registers */
#define CSR_SMEG1_CSR_SMEG1_CNT_CFG_REG                                                                              \
    (CSR_SMEG1_CSR_BASE + 0x70) /* SMEG1 counter configuration register.  This register is used for debug or for \
                                   statistics collection */
#define CSR_SMEG1_CSR_SMEG1_CNT_MATCH_ID_REG                                                                           \
    (CSR_SMEG1_CSR_BASE + 0x74) /* This register is used to configure Instance IDs for all four counters.  This can be \
                                   used for debug or for performance analysis. */
#define CSR_SMEG1_CSR_SMEG1_CNT0_REG \
    (CSR_SMEG1_CSR_BASE +            \
        0x78) /* This smmeg1 counter0 register is a statistics counter that counts API install and engine event0 */
#define CSR_SMEG1_CSR_SMEG1_CNT1_REG                                                                             \
    (CSR_SMEG1_CSR_BASE + 0x80) /* This smeg1 counter1 register is a statistics counter that counts load, store, \
                                   sleep, wakeup, and engine event 1 */
#define CSR_SMEG1_CSR_SMEG1_CNT2_REG \
    (CSR_SMEG1_CSR_BASE +            \
        0x88) /* This smeg1 counter1 register is a statistics counter that counts 'finish' or engine event 2 */
#define CSR_SMEG1_CSR_SMEG1_CNT3_REG \
    (CSR_SMEG1_CSR_BASE +            \
        0x90) /* This smeg1 counter3 register is a statistics counter that counts 'send' and engine event 3 */
#define CSR_SMEG1_CSR_RSV_1_REG (CSR_SMEG1_CSR_BASE + 0x98) /* reserved */
#define CSR_SMEG1_CSR_RSV_2_REG (CSR_SMEG1_CSR_BASE + 0x9C) /* reserved */
#define CSR_SMEG1_CSR_SMEG1_THREAD_ENABLE_CFG2_REG \
    (CSR_SMEG1_CSR_BASE + 0xA0) /* Thread enable configure; bitmap for thread[63:32] of 64 threads in smeg1 */
#define CSR_SMEG1_CSR_RSV_3_REG (CSR_SMEG1_CSR_BASE + 0xA4)             /* reserved */
#define CSR_SMEG1_CSR_RSV_4_REG (CSR_SMEG1_CSR_BASE + 0xA8)             /* reserved */
#define CSR_SMEG1_CSR_RSV_5_REG (CSR_SMEG1_CSR_BASE + 0xAC)             /* reserved */
#define CSR_SMEG1_CSR_RSV_6_REG (CSR_SMEG1_CSR_BASE + 0xB0)             /* reserved */
#define CSR_SMEG1_CSR_SMEG1_TMT_EXT_CFG_REG (CSR_SMEG1_CSR_BASE + 0xB4) /* TIMER engine control info */
#define CSR_SMEG1_CSR_SMEG1_MEM_ECC_ERR_CTP_REG \
    (CSR_SMEG1_CSR_BASE +                       \
        0xB8) /* ecc ERR ADDR; CAPTURE the last err addr;only valid when the ECC interrupt is reported; */
#define CSR_SMEG1_CSR_SMMC_CACHE_RESOURCE_CTP_REG (CSR_SMEG1_CSR_BASE + 0xBC) /* SMMC WQE Cache resource counter */
#define CSR_SMEG1_CSR_SMEG1_SYNC_API_CFG_REG (CSR_SMEG1_CSR_BASE + 0xC0)      /* SYNC_API configuration register */
#define CSR_SMEG1_CSR_RSV_183_REG (CSR_SMEG1_CSR_BASE + 0xC4)                 /* reserved */
#define CSR_SMEG1_CSR_SMEG1_CUR_TIMESTAMP_US_REG (CSR_SMEG1_CSR_BASE + 0xC8)  /* Current timestamp (us) */
#define CSR_SMEG1_CSR_SMEG1_RUNAWAY_THD_CTP_REG                                                                       \
    (CSR_SMEG1_CSR_BASE + 0xD0) /* Each bit represents a runaway thread.  When a thread runs for more than a sampling \
                                   time, it is considered a runaway thread.  Bit63 logs runaway errors for the thread \
                                   63, and bit0 logs the error for the thread 0 respectively. */
#define CSR_SMEG1_CSR_SMEG1_CTP0_REG \
    (CSR_SMEG1_CSR_BASE + 0xD8) /* This is Smart Memory Infra Engine Group1 (SMEG1)snapshot register. */
#define CSR_SMEG1_CSR_SMEG1_CTP1_REG \
    (CSR_SMEG1_CSR_BASE + 0xE0) /* This is Smart Memory Infra Engine Group1 (SMEG1)snapshot register. */
#define CSR_SMEG1_CSR_SMEG1_CTP2_REG \
    (CSR_SMEG1_CSR_BASE + 0xE8) /* This is Smart Memory Infra Engine Group1 (SMEG1)snapshot register. */
#define CSR_SMEG1_CSR_SMEG1_CTP3_REG \
    (CSR_SMEG1_CSR_BASE + 0xF0) /* This is Smart Memory Infra Engine Group1 (SMEG1)snapshot register. */

/* smit_csr Base address of Module's Register */
#define CSR_SMIT_CSR_BASE (0x600)

/* **************************************************************************** */
/*                      smit_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_SMIT_CSR_SMIT_VERSION_REG (CSR_SMIT_CSR_BASE + 0x0) /* reserved for ECO */
#define CSR_SMIT_CSR_SMIT_CFG_REG                                                                                  \
    (CSR_SMIT_CSR_BASE + 0x4) /* This is the Smart Memory Infra Transmission (SMIT) module configuration register. \
                                 The software use this register for debug. */
#define CSR_SMIT_CSR_SMIT_INT_VECTOR_REG (CSR_SMIT_CSR_BASE + 0x8)         /* SMIT interrupt vector */
#define CSR_SMIT_CSR_SMIT_INT_REG (CSR_SMIT_CSR_BASE + 0xC)                /* SMIT interrupt status vector */
#define CSR_SMIT_CSR_SMIT_INT_MASK_REG (CSR_SMIT_CSR_BASE + 0x10)          /* SMIT interrupt mask vector */
#define CSR_SMIT_CSR_SMIT_ERR_PRTY_REG (CSR_SMIT_CSR_BASE + 0x14)          /* RSV */
#define CSR_SMIT_CSR_SMIT_MEM_ECC_CRT_ERR_REG (CSR_SMIT_CSR_BASE + 0x18)   /* tmdr ecc correctable err */
#define CSR_SMIT_CSR_SMIT_MEM_ECC_UNCRT_ERR_REG (CSR_SMIT_CSR_BASE + 0x1C) /* tmdr ecc uncorrectable err */
#define CSR_SMIT_CSR_SMIT_INDRECT_CTRL_REG (CSR_SMIT_CSR_BASE + 0x20)      /* indirect access address registers */
#define CSR_SMIT_CSR_SMIT_INDRECT_TIMEOUT_REG (CSR_SMIT_CSR_BASE + 0x24)   /* memory access timeout configure */
#define CSR_SMIT_CSR_SMIT_INDRECT_DATA_REG (CSR_SMIT_CSR_BASE + 0x28)      /* indirect access data registers */
#define CSR_SMIT_CSR_CFG_MEM_CTRL_BUS0_REG (CSR_SMIT_CSR_BASE + 0x2C)      /* RAM CTRL_BUS寄存器0 */
#define CSR_SMIT_CSR_CFG_MEM_CTRL_BUS1_REG (CSR_SMIT_CSR_BASE + 0x30)      /* RAM CTRL_BUS寄存器1 */
#define CSR_SMIT_CSR_CFG_MEM_CTRL_BUS2_REG (CSR_SMIT_CSR_BASE + 0x34)      /* RAM CTRL_BUS寄存器2 */
#define CSR_SMIT_CSR_CFG_MEM_CTRL_BUS3_REG (CSR_SMIT_CSR_BASE + 0x38)      /* RAM CTRL_BUS寄存器3 */
#define CSR_SMIT_CSR_CFG_MEM_CTRL_BUS4_REG (CSR_SMIT_CSR_BASE + 0x3C)      /* RAM CTRL_BUS寄存器4 */

/* smlc_csr Base address of Module's Register */
#define CSR_SMLC_CSR_BASE (0x700)

/* **************************************************************************** */
/*                      smlc_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_SMLC_CSR_SMLC_VERSION_REG (CSR_SMLC_CSR_BASE + 0x0) /* reserved for ECO */
#define CSR_SMLC_CSR_SMLC_CFG0_REG \
    (CSR_SMLC_CSR_BASE + 0x4) /* Smart Memory Lock Cache Controller (SMLC)  configuration 0. */
#define CSR_SMLC_CSR_SMLC_CFG1_REG \
    (CSR_SMLC_CSR_BASE + 0x8) /* Smart Memory Lock Cache Controller (SMLC)  configuration 1. */
#define CSR_SMLC_CSR_SMLC_CFG2_REG \
    (CSR_SMLC_CSR_BASE + 0xC) /* Smart Memory Lock Cache Controller (SMLC)  configuration 2. */
#define CSR_SMLC_CSR_SMLC_INT_VECTOR_REG \
    (CSR_SMLC_CSR_BASE + 0x10) /* Smart Memory Lock Cache Controller (SMLC) interrupt vector register */
#define CSR_SMLC_CSR_SMLC_INT_REG \
    (CSR_SMLC_CSR_BASE + 0x14) /* Smart Memory Lock Cache Controller (SMLC) interrupt data register */
#define CSR_SMLC_CSR_SMLC_INT_MASK_REG \
    (CSR_SMLC_CSR_BASE + 0x18) /* Smart Memory Lock Cache Controller (SMLC) interrupt mask register. */
#define CSR_SMLC_CSR_SMLC_SRF_OV_ERR_REG (CSR_SMLC_CSR_BASE + 0x1C) /* srf fifo overflow error. */
#define CSR_SMLC_CSR_SMLC_RSV_REG (CSR_SMLC_CSR_BASE + 0x20)
#define CSR_SMLC_CSR_SMLC_ECC_ERR_REG (CSR_SMLC_CSR_BASE + 0x24) /* memory ecc error. */
#define CSR_SMLC_CSR_SMLC_ECC_ERRPR_MASK_REG (CSR_SMLC_CSR_BASE + 0x28)
#define CSR_SMLC_CSR_SMLC_INDRECT_CTRL_REG (CSR_SMLC_CSR_BASE + 0x2C)    /* indirect access address registers */
#define CSR_SMLC_CSR_SMLC_INDRECT_TIMEOUT_REG (CSR_SMLC_CSR_BASE + 0x30) /* memory access timeout configure */
#define CSR_SMLC_CSR_SMLC_INDRECT_DATA_REG (CSR_SMLC_CSR_BASE + 0x34)    /* indirect access data registers */
#define CSR_SMLC_CSR_SMLC_CNT0_REG \
    (CSR_SMLC_CSR_BASE + 0x38) /* Smart Memory Lock Cache Controller (SMLC) event counter0 */
#define CSR_SMLC_CSR_SMLC_CNT1_REG \
    (CSR_SMLC_CSR_BASE + 0x40) /* Smart Memory Lock Cache Controller (SMLC) event counter1 */
#define CSR_SMLC_CSR_SMLC_CNT2_REG \
    (CSR_SMLC_CSR_BASE + 0x48) /* Smart Memory Lock Cache Controller (SMLC) event counter2 */
#define CSR_SMLC_CSR_SMLC_CNT3_REG \
    (CSR_SMLC_CSR_BASE + 0x50) /* Smart Memory Lock Cache Controller (SMLC) event counter3 */
#define CSR_SMLC_CSR_SMLC_CNT_CFG0_REG \
    (CSR_SMLC_CSR_BASE + 0x58) /* Smart Memory Lock Cache Controller (SMLC) event counter configuration 0 */
#define CSR_SMLC_CSR_SMLC_CNT_CFG1_REG \
    (CSR_SMLC_CSR_BASE + 0x5C) /* Smart Memory Lock Cache Controller (SMLC) event counter configuration 1 */
#define CSR_SMLC_CSR_SMLC_CREDIT_CTP_REG \
    (CSR_SMLC_CSR_BASE + 0x60) /* Smart Memory Lock Cache Controller (SMLC)credit snapshot register. */
#define CSR_SMLC_CSR_SMLC_FIFO_DEPTH_CTP_REG \
    (CSR_SMLC_CSR_BASE + 0x64) /* Smart Memory Lock Cache Controller (SMLC)fifo depth snapshot register. */
#define CSR_SMLC_CSR_SMLC_ECC_ERR_CTP_REG \
    (CSR_SMLC_CSR_BASE + 0x68) /* Smart Memory Lock Cache Controller (SMLC)parity error snapshot register. */

/* virtio_smlc_csr Base address of Module's Register */
#define CSR_VIRTIO_SMLC_CSR_BASE (0x2700)

/* **************************************************************************** */
/*                      virtio_smlc_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_VIRTIO_SMLC_CSR_SMLC_VERSION_REG (CSR_VIRTIO_SMLC_CSR_BASE + 0x0) /* reserved for ECO */
#define CSR_VIRTIO_SMLC_CSR_SMLC_CFG0_REG \
    (CSR_VIRTIO_SMLC_CSR_BASE + 0x4) /* Smart Memory Lock Cache Controller (SMLC)  configuration 0. */
#define CSR_VIRTIO_SMLC_CSR_SMLC_CFG1_REG \
    (CSR_VIRTIO_SMLC_CSR_BASE + 0x8) /* Smart Memory Lock Cache Controller (SMLC)  configuration 1. */
#define CSR_VIRTIO_SMLC_CSR_SMLC_CFG2_REG \
    (CSR_VIRTIO_SMLC_CSR_BASE + 0xC) /* Smart Memory Lock Cache Controller (SMLC)  configuration 2. */
#define CSR_VIRTIO_SMLC_CSR_SMLC_INT_VECTOR_REG \
    (CSR_VIRTIO_SMLC_CSR_BASE + 0x10) /* Smart Memory Lock Cache Controller (SMLC) interrupt vector register */
#define CSR_VIRTIO_SMLC_CSR_SMLC_INT_REG \
    (CSR_VIRTIO_SMLC_CSR_BASE + 0x14) /* Smart Memory Lock Cache Controller (SMLC) interrupt data register */
#define CSR_VIRTIO_SMLC_CSR_SMLC_INT_MASK_REG \
    (CSR_VIRTIO_SMLC_CSR_BASE + 0x18) /* Smart Memory Lock Cache Controller (SMLC) interrupt mask register. */
#define CSR_VIRTIO_SMLC_CSR_SMLC_SRF_OV_ERR_REG (CSR_VIRTIO_SMLC_CSR_BASE + 0x1C) /* srf fifo overflow error. */
#define CSR_VIRTIO_SMLC_CSR_SMLC_RSV_REG (CSR_VIRTIO_SMLC_CSR_BASE + 0x20)
#define CSR_VIRTIO_SMLC_CSR_SMLC_ECC_ERR_REG (CSR_VIRTIO_SMLC_CSR_BASE + 0x24) /* memory ecc error. */
#define CSR_VIRTIO_SMLC_CSR_SMLC_ECC_ERRPR_MASK_REG (CSR_VIRTIO_SMLC_CSR_BASE + 0x28)
#define CSR_VIRTIO_SMLC_CSR_SMLC_INDRECT_CTRL_REG \
    (CSR_VIRTIO_SMLC_CSR_BASE + 0x2C) /* indirect access address registers */
#define CSR_VIRTIO_SMLC_CSR_SMLC_INDRECT_TIMEOUT_REG \
    (CSR_VIRTIO_SMLC_CSR_BASE + 0x30) /* memory access timeout configure */
#define CSR_VIRTIO_SMLC_CSR_SMLC_INDRECT_DATA_REG (CSR_VIRTIO_SMLC_CSR_BASE + 0x34) /* indirect access data registers \
                                                                                     */
#define CSR_VIRTIO_SMLC_CSR_SMLC_CNT0_REG \
    (CSR_VIRTIO_SMLC_CSR_BASE + 0x38) /* Smart Memory Lock Cache Controller (SMLC) event counter0 */
#define CSR_VIRTIO_SMLC_CSR_SMLC_CNT1_REG \
    (CSR_VIRTIO_SMLC_CSR_BASE + 0x40) /* Smart Memory Lock Cache Controller (SMLC) event counter1 */
#define CSR_VIRTIO_SMLC_CSR_SMLC_CNT2_REG \
    (CSR_VIRTIO_SMLC_CSR_BASE + 0x48) /* Smart Memory Lock Cache Controller (SMLC) event counter2 */
#define CSR_VIRTIO_SMLC_CSR_SMLC_CNT3_REG \
    (CSR_VIRTIO_SMLC_CSR_BASE + 0x50) /* Smart Memory Lock Cache Controller (SMLC) event counter3 */
#define CSR_VIRTIO_SMLC_CSR_SMLC_CNT_CFG0_REG \
    (CSR_VIRTIO_SMLC_CSR_BASE + 0x58) /* Smart Memory Lock Cache Controller (SMLC) event counter configuration 0 */
#define CSR_VIRTIO_SMLC_CSR_SMLC_CNT_CFG1_REG \
    (CSR_VIRTIO_SMLC_CSR_BASE + 0x5C) /* Smart Memory Lock Cache Controller (SMLC) event counter configuration 1 */
#define CSR_VIRTIO_SMLC_CSR_SMLC_CREDIT_CTP_REG \
    (CSR_VIRTIO_SMLC_CSR_BASE + 0x60) /* Smart Memory Lock Cache Controller (SMLC)credit snapshot register. */
#define CSR_VIRTIO_SMLC_CSR_SMLC_FIFO_DEPTH_CTP_REG \
    (CSR_VIRTIO_SMLC_CSR_BASE + 0x64) /* Smart Memory Lock Cache Controller (SMLC)fifo depth snapshot register. */
#define CSR_VIRTIO_SMLC_CSR_SMLC_ECC_ERR_CTP_REG \
    (CSR_VIRTIO_SMLC_CSR_BASE + 0x68) /* Smart Memory Lock Cache Controller (SMLC)parity error snapshot register. */

/* smmc_f_csr Base address of Module's Register */
#define CSR_SMMC_F_CSR_BASE (0x800)

/* **************************************************************************** */
/*                      smmc_f_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_SMMC_F_CSR_SMMC_F_VERSION_REG (CSR_SMMC_F_CSR_BASE + 0x0) /* reserved for ECO */
#define CSR_SMMC_F_CSR_SMMC_F_MC_CFG_REG (CSR_SMMC_F_CSR_BASE + 0x4)
#define CSR_SMMC_F_CSR_SMMC_F_MC_CFG1_REG (CSR_SMMC_F_CSR_BASE + 0x8)
#define CSR_SMMC_F_CSR_SMMC_HASH_SEED0_REG                                                                            \
    (CSR_SMMC_F_CSR_BASE + 0xC) /* Hash function seed conifg register. This register used to change the original seed \
                                   of hash function. */
#define CSR_SMMC_F_CSR_SMMC_HASH_SEED1_REG                                                                             \
    (CSR_SMMC_F_CSR_BASE + 0x10) /* Hash function seed conifg register. This register used to change the original seed \
                                    of hash function. */
#define CSR_SMMC_F_CSR_SMMC_F_CFG_REG (CSR_SMMC_F_CSR_BASE + 0x14)     /* SMMF_F configuration register . */
#define CSR_SMMC_F_CSR_SMMC_F_MC_INIT_REG (CSR_SMMC_F_CSR_BASE + 0x18) /* SMMC_F main cache initialization */
#define CSR_SMMC_F_CSR_SMMC_F_MC_RF_TIMEOUT_INTERVAL_REG (CSR_SMMC_F_CSR_BASE + 0x1C)
#define CSR_SMMC_F_CSR_SMMC_F_INT_VECTOR_REG \
    (CSR_SMMC_F_CSR_BASE + 0x20) /* Statefull Smart Memory Memory Controller (SMMC_F) interrupt vector register */
#define CSR_SMMC_F_CSR_SMMC_F_INT_REG \
    (CSR_SMMC_F_CSR_BASE + 0x24) /* Smart Memory Memory Controller (SMMC) interrupt data register */
#define CSR_SMMC_F_CSR_SMMC_F_INT_MASK_REG \
    (CSR_SMMC_F_CSR_BASE + 0x28) /* Statefull Smart Memory Memory Controller (SMMC_F) interrupt mask register. */
#define CSR_SMMC_F_CSR_SMMC_F_MC_CACHE_ERR_REG (CSR_SMMC_F_CSR_BASE + 0x2C)
#define CSR_SMMC_F_CSR_SMMC_F_MC_CACHE_MASK_REG (CSR_SMMC_F_CSR_BASE + 0x30)
#define CSR_SMMC_F_CSR_SMMC_F_MC_CACHE_ERR_INFO_REG (CSR_SMMC_F_CSR_BASE + 0x34)
#define CSR_SMMC_F_CSR_SMMC_F_BUFFER_ERR_REG (CSR_SMMC_F_CSR_BASE + 0x38)
#define CSR_SMMC_F_CSR_SMMC_F_BUFFER_MASK_REG (CSR_SMMC_F_CSR_BASE + 0x3C)
#define CSR_SMMC_F_CSR_SMMC_F_BUFFER_ERR_INFO_REG (CSR_SMMC_F_CSR_BASE + 0x40)
#define CSR_SMMC_F_CSR_SMMC_F_BUS_ERR_REG (CSR_SMMC_F_CSR_BASE + 0x44)
#define CSR_SMMC_F_CSR_SMMC_F_BUS_MASK_REG (CSR_SMMC_F_CSR_BASE + 0x48)
#define CSR_SMMC_F_CSR_SMMC_F_MC_MULTI_HIT_ERR_REG (CSR_SMMC_F_CSR_BASE + 0x4C)
#define CSR_SMMC_F_CSR_SMMC_F_VC_CACHE_ERR_REG (CSR_SMMC_F_CSR_BASE + 0x50)
#define CSR_SMMC_F_CSR_SMMC_F_VC_CACHE_MASK_REG (CSR_SMMC_F_CSR_BASE + 0x54)
#define CSR_SMMC_F_CSR_SMMC_F_VC_CACHE_ERR_INFO_REG (CSR_SMMC_F_CSR_BASE + 0x58)
#define CSR_SMMC_F_CSR_SMMC_F_INDRECT_CTRL_REG (CSR_SMMC_F_CSR_BASE + 0x5C)    /* indirect access address registers */
#define CSR_SMMC_F_CSR_SMMC_F_INDRECT_TIMEOUT_REG (CSR_SMMC_F_CSR_BASE + 0x60) /* memory access timeout configure */
#define CSR_SMMC_F_CSR_SMMC_F_INDRECT_DATA_REG (CSR_SMMC_F_CSR_BASE + 0x64)    /* indirect access data registers */
#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT_ENB_REG (CSR_SMMC_F_CSR_BASE + 0x68)      /* counter enable */
#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT_EVENT_SEL_ENB_GRP0_REG \
    (CSR_SMMC_F_CSR_BASE + 0x6C) /* counter event selection enable */
#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT_EVENT_SEL_ENB_GRP1_REG \
    (CSR_SMMC_F_CSR_BASE + 0x70) /* counter event selection enable */
#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT_EVENT_SEL0_REG (CSR_SMMC_F_CSR_BASE + 0x74)
#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT_EVENT_SEL1_REG (CSR_SMMC_F_CSR_BASE + 0x78)
#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT_EVENT_SEL2_REG (CSR_SMMC_F_CSR_BASE + 0x7C)
#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT_EVENT_SEL3_REG (CSR_SMMC_F_CSR_BASE + 0x80)
#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT_EVENT_SEL4_REG (CSR_SMMC_F_CSR_BASE + 0x84)
#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT_EVENT_SEL5_REG (CSR_SMMC_F_CSR_BASE + 0x88)
#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT_EVENT_SEL6_REG (CSR_SMMC_F_CSR_BASE + 0x8C)
#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT_EVENT_SEL7_REG (CSR_SMMC_F_CSR_BASE + 0x90)
#define CSR_SMMC_F_CSR_SMMC_F_MC_STATUS_REG (CSR_SMMC_F_CSR_BASE + 0x94)
#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT0_REG                                                                             \
    (CSR_SMMC_F_CSR_BASE +                                                                                            \
        0x98) /* This SMMC main cache counter0 register is a dynamic counter to count any event that is configured by \
                 SMMC_F_MC_CNT_EVENT_SEL_ENB0 and SMMC_F_MC_CNT_EVENT_SEL0. */
#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT1_REG                                                                             \
    (CSR_SMMC_F_CSR_BASE +                                                                                            \
        0xA0) /* This SMMC main cache counter0 register is a dynamic counter to count any event that is configured by \
                 SMMC_F_MC_CNT_EVENT_SEL_ENB1 and SMMC_F_MC_CNT_EVENT_SEL1. */
#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT2_REG                                                                             \
    (CSR_SMMC_F_CSR_BASE +                                                                                            \
        0xA8) /* This SMMC main cache counter0 register is a dynamic counter to count any event that is configured by \
                 SMMC_F_MC_CNT_EVENT_SEL_ENB2 and SMMC_F_MC_CNT_EVENT_SEL2. */
#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT3_REG                                                                             \
    (CSR_SMMC_F_CSR_BASE +                                                                                            \
        0xB0) /* This SMMC main cache counter0 register is a dynamic counter to count any event that is configured by \
                 SMMC_F_MC_CNT_EVENT_SEL_ENB3 and SMMC_F_MC_CNT_EVENT_SEL3. */
#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT4_REG                                                                             \
    (CSR_SMMC_F_CSR_BASE +                                                                                            \
        0xB8) /* This SMMC main cache counter0 register is a dynamic counter to count any event that is configured by \
                 SMMC_F_MC_CNT_EVENT_SEL_ENB4 and SMMC_F_MC_CNT_EVENT_SEL4. */
#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT5_REG                                                                             \
    (CSR_SMMC_F_CSR_BASE +                                                                                            \
        0xC0) /* This SMMC main cache counter0 register is a dynamic counter to count any event that is configured by \
                 SMMC_F_MC_CNT_EVENT_SEL_ENB5 and SMMC_F_MC_CNT_EVENT_SEL5. */
#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT6_REG                                                                             \
    (CSR_SMMC_F_CSR_BASE +                                                                                            \
        0xC8) /* This SMMC main cache counter0 register is a dynamic counter to count any event that is configured by \
                 SMMC_F_MC_CNT_EVENT_SEL_ENB6 and SMMC_F_MC_CNT_EVENT_SEL6. */
#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT7_REG                                                                             \
    (CSR_SMMC_F_CSR_BASE +                                                                                            \
        0xD0) /* This SMMC main cache counter0 register is a dynamic counter to count any event that is configured by \
                 SMMC_F_MC_CNT_EVENT_SEL_ENB7 and SMMC_F_MC_CNT_EVENT_SEL7. */
#define CSR_SMMC_F_CSR_SMMC_F_VC_FIFO_DEPTH0_REG \
    (CSR_SMMC_F_CSR_BASE + 0xD8) /* SMMC_F victim cache FIFO depth or   credit */
#define CSR_SMMC_F_CSR_SMMC_F_VC_FIFO_DEPTH1_REG \
    (CSR_SMMC_F_CSR_BASE + 0xDC) /* SMMC_F victim cache FIFO depth or   credit */
#define CSR_SMMC_F_CSR_SMMC_F_MC_FIFO1_DEPTH_REG \
    (CSR_SMMC_F_CSR_BASE + 0xE0) /* SMMC_F main cache FIFO depth or   credit */
#define CSR_SMMC_F_CSR_SMMC_F_MC_FIFO2_DEPTH_REG (CSR_SMMC_F_CSR_BASE + 0xE4) /* SMMC_F main cache FIFO depth */
#define CSR_SMMC_F_CSR_SMMC_F_ERR_INJ_REG (CSR_SMMC_F_CSR_BASE + 0xE8)
#define CSR_SMMC_F_CSR_SMMC_F_GPA_TRANS_ERR_REG (CSR_SMMC_F_CSR_BASE + 0xEC)
#define CSR_SMMC_F_CSR_SMMC_F_QU_INTF_CNT_CFG_REG (CSR_SMMC_F_CSR_BASE + 0xF0)
#define CSR_SMMC_F_CSR_SMMC_F_QU_INTF_RX_CNT_REG (CSR_SMMC_F_CSR_BASE + 0xF4)
#define CSR_SMMC_F_CSR_SMMC_F_QU_INTF_TX_CNT_REG (CSR_SMMC_F_CSR_BASE + 0xF8)
#define CSR_SMMC_F_CSR_SMMC_F_MC_CFG2_REG (CSR_SMMC_F_CSR_BASE + 0xFC)

/* smmc_l_csr Base address of Module's Register */
#define CSR_SMMC_L_CSR_BASE (0x900)

/* **************************************************************************** */
/*                      smmc_l_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_SMMC_L_CSR_SMMC_L_VERSION_REG (CSR_SMMC_L_CSR_BASE + 0x0)          /* reserved for ECO */
#define CSR_SMMC_L_CSR_SMMC_L_CFG_REG (CSR_SMMC_L_CSR_BASE + 0x4)              /* SMMC_L configure register */
#define CSR_SMMC_L_CSR_SMMC_L_STAT_REG (CSR_SMMC_L_CSR_BASE + 0x8)             /* SMMC_L status register */
#define CSR_SMMC_L_CSR_SMMC_L_INT_VECTOR_REG (CSR_SMMC_L_CSR_BASE + 0xC)       /* SMMC_L interrupt vector register */
#define CSR_SMMC_L_CSR_SMMC_L_INT_REG (CSR_SMMC_L_CSR_BASE + 0x10)             /* SMMC_L interrupt register */
#define CSR_SMMC_L_CSR_SMMC_L_INT_MASK_REG (CSR_SMMC_L_CSR_BASE + 0x14)        /* SMMC_L interrupt mask register */
#define CSR_SMMC_L_CSR_SMMC_L_MEM_ERR_REG (CSR_SMMC_L_CSR_BASE + 0x18)         /* SMMC_L MEM error register */
#define CSR_SMMC_L_CSR_SMMC_L_MEM_ERR_MASK_REG (CSR_SMMC_L_CSR_BASE + 0x1C)    /* SMMC_L MEM error mask register */
#define CSR_SMMC_L_CSR_SMMC_L_MEM_ERR_INFO_REG (CSR_SMMC_L_CSR_BASE + 0x20)    /* SMMC_L MEM error info register */
#define CSR_SMMC_L_CSR_SMMC_L_INDRECT_CTRL_REG (CSR_SMMC_L_CSR_BASE + 0x24)    /* indirect access address registers */
#define CSR_SMMC_L_CSR_SMMC_L_INDRECT_TIMEOUT_REG (CSR_SMMC_L_CSR_BASE + 0x28) /* memory access timeout configure */
#define CSR_SMMC_L_CSR_SMMC_L_INDRECT_DATA_REG (CSR_SMMC_L_CSR_BASE + 0x2C)    /* indirect access data registers */
#define CSR_SMMC_L_CSR_SMMC_L_CNT_CFG_REG (CSR_SMMC_L_CSR_BASE + 0x30)         /* SMMC_L counter configure register */
#define CSR_SMMC_L_CSR_SMMC_L_CNT_MATCH_BANK_REG \
    (CSR_SMMC_L_CSR_BASE + 0x34) /* SMMC_L counter configure register for matching instance ID */
#define CSR_SMMC_L_CSR_SMMC_L_CNT_MATCH_INSTANCE_REG \
    (CSR_SMMC_L_CSR_BASE + 0x38) /* SMMC_L counter configure register for matching instance ID */
#define CSR_SMMC_L_CSR_SMMC_L_CNT0_REG (CSR_SMMC_L_CSR_BASE + 0x3C) /* SMMC_L counter 0 register */
#define CSR_SMMC_L_CSR_SMMC_L_CNT1_REG (CSR_SMMC_L_CSR_BASE + 0x40) /* SMMC_L counter 1 register */
#define CSR_SMMC_L_CSR_SMMC_L_CNT2_REG (CSR_SMMC_L_CSR_BASE + 0x44) /* SMMC_L counter 2 register */
#define CSR_SMMC_L_CSR_SMMC_L_CNT3_REG (CSR_SMMC_L_CSR_BASE + 0x48) /* SMMC_L counter 3 register */
#define CSR_SMMC_L_CSR_SMMC_L_BANK_QUEUE_DEPTH_CTP0_REG \
    (CSR_SMMC_L_CSR_BASE + 0x4C) /* SMMC_L bank queue's depth register 0 */
#define CSR_SMMC_L_CSR_SMMC_L_BANK_QUEUE_DEPTH_CTP1_REG \
    (CSR_SMMC_L_CSR_BASE + 0x50)                                           /* SMMC_L bank queue's depth register 1 */
#define CSR_SMMC_L_CSR_SMMC_L_ECC_INJ_CFG_REG (CSR_SMMC_L_CSR_BASE + 0x54) /* SMMC_L ECC inject register */
#define CSR_SMMC_L_CSR_SMMC_L_PG_CFG_REG (CSR_SMMC_L_CSR_BASE + 0x58)      /* SMMC_L Partial Good register */

#endif // SM_REG_OFFSET_H
